1. Field of the Invention
The invention relates to a class D amplifier that converts PCM (Pulse Code Modulation) sound (musical tone) data into a PWM (Pulse Width Modulation) signal to be amplified and output, and particularly to a class D amplifier that is designed to reduce output noise
2. Description of Related Art
As is well known, in this type of D class amplifier, jitter within the clocks for a PWM conversion appears as output noise as it is. An arithmetic error such as discarding lower bits in the digital process at a PWM conversion contributes to output noise. In a class D amplifier in prior art, as described in Japanese Patent Publication Sho 59-183510, an output of a class D amplifier is filtered through a low pass filter so that it may be converted to an analog signal to be supplied to a load (a speaker). At the same time, the analog signal is converted to a digital signal to be fedback to an input side. However, this type of processing has a drawback that it requires a high precision A/D (analog to digital) converter, which increases the cumber of components and makes a circuit complex and expensive.
An amplifier has been in actual use that converts PCM sound data (“sound” here means general sound including such as musical tone, without being limited to the so-human sound) to an analog signal, which in turn is converted to a PWM signal. This amplifier, which performs analog processing, can easily feedback an output. But, there is a problem in that when PWM is performed by an analog processing, it is susceptible to an extraneous signal and a signal such as input digital data.
Japanese Patent Publication 2000-196374 (Patent Number 3445177) discloses a class D amplifier that uses ΔΣ modulation. However, since this class D amplifier makes use of ΔΣ modulation, there is a defect that higher frequencies are required, with low power efficiency. Moreover, there is another drawback that proper feedback cannot be performed, because a feedback signal taken at an output of-a constant voltage switch is asynchronous with an input clock.
A class D amplifier will be explained that uses only digital processing in prior art.
FIG. 17 is a block diagram for illustrating a structure of a D class amplifier in prior art. In the figure, reference numeral 1 denotes an adder for receiving and adding PCM sound data PD; reference numeral 2 designates a PWM circuit for converting sound data from the adder 1 to a PWM signal; and reference numeral 3 is a feedback circuit H(z) for eliminating quantization noise.
Here, quantization noise is one that is produced because of a limitation in resolution of the PWM circuit 2. For example, in a case where PCM sound data is comprised of 16 bits and the resolution of the PWM circuit 2 is 10 bits, the lower 6 bits of the 16 bits from the adder 1 is input to the feedback circuit H(z) 3 as quantization noise. The feedback circuit H(z) 3, which is comprised of an integration circuit (FIR filter), is a circuit so that a transfer function of an PWM output is 1/(1-H(z)). Output data from the feedback circuit 3 is added to the PCM sound data at the adder 1, which can suppress quantization noise in lower frequencies to increase resolution.
Reference numeral 4 is a multiplier that receives a sampling signal SL synchronized with the PCM sound data. The multiplier 4 consists of a PLL (Phase Locked Loop) to output a pulse signal with a frequency multiplied by the frequency of the sampling signal SL. Reference numeral 5 is an oscillator to produce a sawtooth (or a triangle wave) carrier signal (digital signal) Pct, based on a pulse signal from the multiplier 4, that sequentially increases from 0 to a constant value at which it is reset. The carrier signal Pct is applied to the PWM circuit 2, which generates a PWM signal that rises at a reset time of the carrier signal Pct and falls at a time when the carrier signal Pct agrees with output data from the adder. The PWM signal is furnished to an output switching circuit 6, which in turn amplifies an output from the PWM circuit 2 to be applied to a load (speaker) through a low pass filter.
In the class D amplifier described above, since the multiplier 4 comprised of a PLL is used, jitter is tend to be produced to become output noise. There are many cases where the sampling signal provided from outside includes noise that also generates jitter.
Japanese Utility Model Publication Hei 3-36099 is known as a literature of prior art concerning a class D amplifier.
Accordingly, there is a need to reduce noise in a class D amplifier.